VIA Apollo MVP3 chipset press release

For the sake of keeping it somewhere, here is the VIA Apollo MVP3 chipsetĀ press release…

The Apollo MVP3 is a high performance, cost effective, and energy efficient chip set for the implementation of AGP, PCI, and ISA in desktop and notebook personal computer systems from 66 MHz to 100 MHz based on 64 bit Socket-7 super-scalar processors.

The Apollo MVP3 chipset consists of the VT82C598AT system controller (476 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP). The VT82C598AT system controller provides superior performance between the CPU, optional synchronous cache, DRAM, AGP bus, and the PCI bus with pipelined, burst, and concurrent operation. The DRAM controller supports standard Fast page Mode (FPM), EDO, SDRAM, and DDR SDRAM. The VT82C598AT complies with the Accelerated Graphics Port Specification 1.0 and features support for 66/75/83/100 MHz CPU bus frequencies and the 66 MHz AGP bus frequency. Coupled with BDDR SDRAM II, the VT82C598AT allows implementation of the most flexible, reliable, and high-performance DRAM interface.

KEY FEATURES
Supports 66 / 75 / 83 / 100 MHz CPU external bus speed
PC97 compatible using VT82C586B South Bridge with ACPI Power Management
Includes UltraDMA-33 EIDE, USB, and Keyboard/PS2-Mouse Interfaces plus RTC/CMOS on chip
Single chip implementation for 64 bit Socket-7 CPU, 64 bit system memory, 32 bit PCI and 32 bit AGP interfaces
3.3V and sub-3.3V interface to CPU
3.3V (5V tolerant) DRAM, AGP,and PCI interface
AGP v1.0 compliant
PCI buses are synchronous/pseudo-synchronous to host CPU bus
33 MHz operation on the primary PCI bus
66 MHz PCI operation on the AGP bus
Concurrent CPU and AGP access
FP, EDO, SDRAM, and DDR SDRAM
Consists of the VT82C598AT system controller (476 pin BGA) and the VT82C586B PCI to ISA bridge (208 pin PQFP)
Built-in NAND-tree pin scan test capability
0.35um, high speed and low power CMOS process

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